HT16270
RAM Mapping 64 16 LCD Controller for I/O mC
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Crystal Osc.
1
April 21, 2000
Features
Operating voltage: 2.7V~5.2V
External Crystal 32.768kHz oscillator
1/5 bias, 1/16 duty, frame frequency is 64Hz
Max. 6416 patterns, 16 commons,
64 segments
Built-in internal resistor type bias generator
3-wire serial interface
8 kinds of time base/WDT selection
Time base or WDT overflow output
Built-in LCD display RAM
R/W address auto increment
Two selectable buzzer frequencies
(2kHz/4kHz)
Power down command reduces power
consumption
Software configuration feature
Data mode and Command mode instructions
Three data accessing modes
VLCD pin to adjust LCD operating voltage
General Description
HT16270 is a peripheral device specially de-
signed for I/O type mC used to expand the dis-
play capability. The max. display segment of
the device are 1024 patterns (6416). It also
supports serial interface, buzzer sound, watch-
dog timer or time base timer functions. The
HT16270 is a memory mapping and
multi-function LCD controller. The software
configuration feature of the HT16270 make it
suitable for multiple LCD applications includ-
ing LCD modules and display subsystems. Only
three lines are required for the interface be-
tween the host controller and the HT16270.
The HT162X series have many kinds of prod-
ucts that match various applications.
Block Diagram
Pin Assignment
HT16270
2
April 21, 2000
C S
R D
W R
D A T A
V S S
O S C I
O S C O
V D D
V L C D
I R Q
B Z
B Z
T 1
T 2
T 3
T 4
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 5
C O M 6
C O M 7
C O M 8
C O M 9
C O M 1 0
C O M 1 1
C O M 1 2
N C
S E G 4 3
S E G 4 2
N C
S E G 4 1
S E G 4 0
S E G 3 9
S E G 3 8
S E G 3 7
S E G 3 6
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
N C
N C
S E G 1 8
S E G 1 7
SEG
1
6
SEG
1
5
SEG
1
4
SEG
1
3
SEG
1
2
SEG
1
1
SEG
1
0
SEG
9
SEG
8
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
CO
M
1
5
CO
M
1
4
CO
M
1
3
SEG
4
4
SEG
4
5
SEG
4
6
SEG
4
7
SEG
4
8
SEG
4
9
SEG
5
0
SEG
5
1
SEG
5
2
SEG
5
3
SEG
5
4
SEG
5
5
SEG
5
6
SEG
5
7
SEG
5
8
SEG
5
9
SEG
6
0
SEG
6
1
SEG
6
2
SEG
6
3
H T 1 6 2 7 0
1 0 0 Q F P
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
9 6
9 7
9 8
9 9
1 0 0
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
W a t c h d o g T i m e r
a n d
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C I
C S
R D
C O M 0
C O M 1 5
S E G 0
S E G 6 3
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
I R Q
V S S
V D D
V L C D
O S C O
Pad Assignment
Chip size: 245 237 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT16270
3
April 21, 2000
1
4 9
2
5 0
3
5 1
4
5 2
5
5 3
6
5 4
7
5 5
8
5 6
9
5 7
1 0
5 8
1 1
5 9
1 2
6 0
1 3
6 1
1 4
6 2
1 5
6 3
1 6
6 4
1 7
6 5
1 8
6 6
1 9
6 7
2 0
6 8
2 1
6 9
2 2
7 0
2 3 2 4
2 5
7 3
2 6
7 4
2 7
7 5
2 8
7 6
2 9
7 7
3 0
7 8
3 1
7 9
3 2
8 0
3 3
8 1
3 4
8 2
3 5
8 3
3 6
8 4
3 7
8 5
3 8
8 6
3 9
8 7
4 0
8 8
4 1
8 9
4 2
9 0
4 3
9 1
4 4
9 2
9 3
4 6
9 4
4 7
9 5
4 8
9 6
7 2
7 1
4 5
D A T A
V S S
O S C I
O S C O
V D D
V L C D
I R Q
B Z
B Z
T 1
T 2
T 3
T 4
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 5
C O M 6
C O M 7
C O M 8
C O M 9
SE
G
1
8
SE
G
1
7
SE
G
1
6
SE
G
1
5
SE
G
1
4
SE
G
1
3
SE
G
1
2
SE
G
1
1
SE
G
1
0
SE
G
9
SE
G
8
SE
G
7
SE
G
6
SE
G
5
SE
G
4
SE
G
3
SE
G
2
SE
G
1
SE
G
0
CO
M
1
5
CO
M
1
4
CO
M
1
3
CO
M
1
2
CO
M
1
1
CO
M
1
0
S E G 4 1
S E G 4 0
S E G 3 9
S E G 3 8
S E G 3 7
S E G 3 6
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
SE
G
4
2
SE
G
4
3
SE
G
4
4
SE
G
4
5
SE
G
4
6
SE
G
4
7
SE
G
4
8
SE
G
4
9
SE
G
5
0
SE
G
5
1
SE
G
5
2
SE
G
5
3
SE
G
5
4
SE
G
5
5
SE
G
5
6
SE
G
5
7
SE
G
5
8
SE
G
5
9
SE
G
6
0
SE
G
6
1
SE
G
6
2
SE
G
6
3
RD
WR
( 0 , 0 )
CS
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
-116.57
99.90
49
116.15
-99.79
2
-116.68
90.80
50
116.15
-93.16
3
-116.72
84.15
51
116.19
-81.18
4
-116.72
77.50
52
116.19
-74.54
5
-116.72
70.90
53
116.15
-62.58
6
-115.93
64.25
54
116.19
-55.93
7
-116.72
54.75
55
116.19
-43.94
8
-116.72
41.45
56
116.19
-37.40
9
-116.72
21.85
57
116.19
-25.37
10
-115.94
11.39
58
116.19
-18.70
11
-115.94
-0.60
59
116.19
-6.72
12
-115.94
-7.18
60
116.24
-0.09
13
-115.90
-19.21
61
116.24
11.90
14
-115.97
-25.85
62
116.19
18.49
15
-115.93
-37.85
63
116.24
30.51
16
-115.93
-44.45
64
116.19
37.10
17
-115.93
-56.45
65
116.19
49.09
18
-115.93
-63.05
66
116.15
55.76
19
-115.97
-75.05
67
116.15
67.75
20
-115.93
-81.70
68
116.19
74.38
21
-115.93
-93.65
69
116.15
86.36
22
-115.94
-100.30
70
116.19
93.03
23
-115.94
-112.37
71
116.11
104.85
24
-108.08
-112.07
72
112.20
112.24
25
-96.03
-112.05
73
100.04
112.24
26
-89.43
-112.05
74
93.42
112.24
27
-77.43
-112.05
75
81.43
112.24
28
-70.82
-112.05
76
74.80
112.24
29
-58.83
-112.05
77
62.77
112.24
30
-52.17
-112.05
78
56.23
112.24
31
-40.22
-112.05
79
44.20
112.24
32
-33.58
-112.05
80
37.57
112.24
33
-21.58
-112.00
81
25.63
112.24
34
-14.98
-112.05
82
18.95
112.24
35
-2.97
-112.00
83
6.97
112.24
36
3.67
-112.05
84
0.38
112.24
37
15.63
-112.05
85
-11.65
112.24
38
22.27
-112.05
86
-18.23
112.20
39
34.28
-112.05
87
-30.22
112.24
40
40.88
-112.05
88
-36.89
112.24
41
52.88
-112.05
89
-48.92
112.24
42
59.47
-112.05
90
-55.51
112.24
43
71.47
-112.00
91
-67.45
112.29
44
78.13
-112.00
92
-74.12
112.24
45
90.07
-112.05
93
-86.15
112.24
46
96.72
-112.05
94
-92.72
112.25
47
108.72
-112.00
95
-104.72
112.25
48
116.19
-111.82
96
-114.22
112.25
HT16270
4
April 21, 2000
Pad Description
Pad No.
Pad Name
I/O
Description
1
DATA
I/O Serial data input/output with pull-high resistor
2
VSS
Negative power supply, ground
3
OSCI
I
Crystal oscillator input pin
4
OSCO
O Crystal oscillato output pin
5
VDD
Positive power supply
6
VLCD
I
LCD operating voltage input pad.
7
IRQ
O Time base or watchdog timer overflow flag, NMOS open drain
output
8, 9
BZ, BZ
O 2kHz or 4kHz tone frequency output pair (Tristate output
buffer)
10~13
T1~T4
I
Not connected
14~29
COM0~COM15
O LCD common outputs
30~93
SEG0~SEG63
O LCD segment outputs
94
CS
I
Chip selection input with pull-high resistor. When the CS is
logic high, the data and command read from or write to the
HT16270 are disabled. The serial interface circuit is also reset.
But if the CS is at logic low level and is input to the CS pad, the
data and command transmission between the host controller
and the HT16270 are all enabled.
95
RD
I
READ clock input with pull-high resistor. Data in the RAM of
the HT16270 are clocked out on the rising edge of the RD sig-
nal. The clocked out data will appear on the data line. The host
controller can use the next falling edge to latch the clocked out
data.
96
WR
I
WRITE clock input with pull-high resistor. Data on the DATA
line are latched into the HT16270 on the rising edge of the WR
signal.
Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V
Storage Temperature.................-50C to 125C
Input Voltage.................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
HT16270
5
April 21, 2000
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